Tandem NonStop Cyclone

The Tandem NonStop Cyclone was the high-end culmination of the original proprietary TNS processor family. Its ECL processor could issue paired operations and delivered around 10 MIPS per processor, giving large transaction-processing customers substantially greater capacity.

Processors were organised in four-CPU sections connected through fibre-optic Dynabus technology. Guardian software, NonStop SQL and Tandem’s process-pair model allowed systems to grow while applications continued to run.

Notable Features

• The microcoded superscalar processor could complete common pairs of stack instructions during one cache cycle.
• Each processor delivered approximately 10 MIPS, several times the performance of the earlier VLX.
• Four-processor sections used fibre-optic connections to build large systems.

Historical Significance

• Cyclone brought the original Tandem instruction set to mainframe-class performance at the end of the 1980s.
• It served major financial, telecommunications and reservation workloads where downtime was unacceptable.

Collector’s Notes

• Cyclone installations were large, expensive and highly customised, making complete surviving systems uncommon.
• Black cabinets, processor sections, fibre interconnects and paired disk hardware together define the original configuration.

Specifications

Technical Information
Name	Tandem NonStop Cyclone
Manufacturer	Tandem Computers
Launched	Tuesday, October 17, 1989
Discontinued	Mid-1990s
Country	United States
CPU	Tandem proprietary Cyclone processor
Units Sold
Power	Redundant, serviceable system power supplies; requirements depended on cabinet configuration
Fault Tolerance	Self-checking CPUs, process pairs, redundant fibre paths, mirrored disks and online serviceability
Architecture	Superscalar ECL implementation of the proprietary TNS stack architecture
Networking	Expand networking, Ethernet, X.25, SNA and fibre-linked NonStop clustering
Operating System	Guardian 90 / NonStop Kernel with NonStop SQL
Expansion / I/O	Fibre-connected four-processor sections with duplicated system paths
Keyboard	External operator console terminal keyboard
Storage	Large mirrored disk farms and tape subsystems with redundant high-speed controllers
Sound	No general-purpose sound hardware
Graphics	Terminal-oriented text output; no integrated graphics subsystem
Display	External operator console terminal; no integrated display
ROM	Boot, diagnostic and processor microcode storage; capacity varied by generation and configuration
RAM	Protected private memory per processor with large distributed totals
CPU Speed	45 ns cache cycle; approximately 10 MIPS per processor